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fedl9479e-02 issue date: apr. 3, 2013 ML9479E static, 1/2 duty, 1/3 duty, 1/4 duty 160 outputs lcd driver 1/32 general description the ML9479E is an lcd driver lsi, consists of a 160-bit shift register, a 640-bit data latch, 160 sets of lcd drivers, and a common signal generation circuit. it can directly drive an lcd up to 160 segments for static display, 320 segments for 1/2-duty display, 480 segments for 1/3-duty display, and 640 segments for 1/4-duty display. the three-wire serial interface and i 2 c interface are selectable. features ? ? logic power supply voltage : 2.7 to 5.5 v ? lcd drive power supply voltage : 4.5 to 5.5 v ? maximum number of segments static display : 160 segments 1/2-duty display : 320 segments 1/3-duty display : 480 segments 1/4-duty display : 640 segments ? interface with microcomputer : serial interface : data, clock, load clock transfer speed up to 1 mhz i 2 c interface : sda, scl, sdaack scl transfer speed up to 400 khz ? built-in cr oscillator circuit using the internal resistor or external resistor ? cascade connectable (up to eight chips) ? built-in common signal generation circuit ? built-in common output intermediate-value voltage generation circuit ? built-in poc (power on clear) circuit ? gold bump chip (ML9479Edvwa)
fedl9479e-02 ML9479E 2/32 block diagram 160-dot segment driver latch selector load osc 160-bit latch1 data (sda) clock (scl) bias vdd gnd timing generator 160-ch data selector comon driver seg1 seg160 com1 160-bit shift register 160 com2 com3 com4 duty0 160 160 160 160 vlcd bias resi. osc i/e oscr osc1 osc2 duty1 resetb command decoder sdaack sa0 a1 a0 cko syncb m/s poc i2c test1 test2 poceb 160-bit latch2 160-bit latch3 160-bit latch4
fedl9479e-02 ML9479E 3/32 absolute maximum ratings item symbol condition rating unit logic power supply voltage v dd ta = 25c -0.3 to 6.0 v lcd drive power supply voltage v lcd ta = 25c - 0.3 to 6.0 v input voltage v i ta = 25c ? 0.3 to v dd + 0.3 v output short-circuit current is ta = 25c - 2.0 to +2.0 ma chip temperature tc ? 125 c storage temperature t stg ? -55 to +150 c note: do not use the ML9479E by short-circuiting one output pin to another output pin as well as to other pin (input pin, input/output pin, or power supply pin). recommended operation conditions item symbol condition range unit logic power supply voltage v dd * ? 2.7 to 5.5 v lcd drive power supply voltage v lcd * ? 4.5 to 5.5 v osc in clock frequency f cp1 ? up to 10 khz data clock frequency f cp2 ? up to 1.0 mhz scl clock frequency f scl ? up to 400 khz operating temperature t a ? -40 to +105 c note(*): use at v dd ? v lcd . the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 recommended setting range for external component (oscillator circuit) (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= ?40 to +105c) item symbol condition min typ max unit oscillation resistor r f ? 423 470 517 k ? frame frequency f frm (f1,f0)=(0,1) 47 75 114 hz the relation between oscillation resistor and frame frequency is as the equation below. f frm = f osc /(16 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25%
fedl9479e-02 ML9479E 4/32 electrical characteristics dc characteristics (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin "h" input voltage v ih ? 0.8v dd ? v dd v (*1) "l" input voltage v il ? gnd ? 0.2v dd v (*1) input leakage current 1 i l1 v i = v dd or 0 v -1.0 ? 1.0 a (*1) input leakage current 2 i l2 v i = v dd or 0v poceb="h" -1.0 ? 1.0 a resetb pull-up current i pu v dd = 5.0v,v i = 0 v poceb = "l" 30 ? 140 a resetb "h" output voltage v oh i o = -600 a 0.9v dd ? ? v ? cko, syncb "l" output voltage 1 v ol1 i o = 600 a ? ? 0.1v dd v cko, syncb "l" output voltage 2 v ol2 i o = 600 a ? ? 0.1v dd v sdaack segment v ohs v lcd = 5v ? 5 15 k ? seg1 to seg160 driver on resistor common v ohc v lcd = 5v ? 5 12 k ? com 1 to com4 (*1) : data(sda), clock(scl), load, m/s, syncb, duty1, duty0, bias, sa0, a1, a0, osc1, osc i/e, i2c, poceb (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin i dds ? 8 15 a vdd static supply current i lcds v dd =v lcd =5.5 v input pin fixed to "h" or "l" oscillation stopped, output no-load poceb="l" ? 9 15 a vlcd i dd1 (*6) ? 10 18 a vdd dynamic supply current 1 i lcd1 v dd =v lcd = 5.5 v (*2)(*3) clock osc1 external input f cp1 =1.8khz (*7) ? 9 15 a vlcd i dd2 (*6) ? 65 90 a vdd dynamic supply current 2 i lcd2 v dd =v lcd = 5.5 v (*2)(*3) internal oscillation (*7) ? 9 15 a vlcd i dd3 ? 200 300 a vdd dynamic supply current 3 i lcd3 v dd =v lcd = 5.5 v (*2)(*4)(*6) internal oscillation at three-wire serial if data input ? 9 15 a vlcd i dd4 ? 230 350 a vdd dynamic supply current 4 i lcd4 v dd =v lcd = 5.5 v (*2)(*5)(*6) internal oscillation at i 2 c if data input ? 9 15 a vlcd (*2) : m/s = "h", 1/4-duty, 1/3-bias, (f1,f0) = (1,1) 95 hz, poceb = "l", output pin no-load. (*3) : three-wire serial or i 2 c interface. input pin fixed to "h" or "l". (*4) : serial interface, data input frequency = 1 mhz. (*5) : i 2 c interface, data input frequency = 400 khz. (*6) : alternately inputs "0" and "1" for lcd display data (checkered display). (*7) : inputs all "1s" for lcd display data (all illuminated).
fedl9479e-02 ML9479E 5/32 switching characteristics ? osc ti ming (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin osc in clock frequency (external input) f cp1 ? 1.8 10 khz osc1 clock pulse width (external input) t wcp1 40 ? ? s osc1 clock rise and fall time (external input) t osc clock input from osc1. osc2 and oscr open. osc i/e = "l" ? ? (*1) s osc1 external rf clock frequency (internal oscillation) f osc1 between osc1 and osc2 r f = 470k ? (f1,f0)=(0,1) oscr open. osc i/e = "h" 18 28.8 44 khz osc1, osc2 internal clock frequency (internal oscillation) f osc2 osc1 open. (f1,f0)=(0,1) osc2 and oscr short-circuited. osc i/e = "h" 18 28.8 44 khz osc1, oscr, osc2 the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 (*1) t osc is a reference value. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=2 s. ? serial interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin data clock frequency f cp2 ? ? 1 mhz clock data clock pulse width t wcp2 100 ? ? ns clock data setup time t su 50 ? ? ns data data hold time t hd 50 ? ? ns clock clock-load timing t cl 100 ? ? ns clock load-clock timing t lc 100 ? ? ns load load pulse width t wld 100 ? ? ns load signal rise and fall time tsr,tsf ? ? (*2) ns ? clock,data, load (*2) tsr and tsf shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=10ns.
fedl9479e-02 ML9479E 6/32 ? i 2 c interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin scl clock frequency f scl ? ? 400 khz scl hold time (repeat) "statrt" condition t hd,sta 0.6 ? ? s scl,sda scl "l" pulse width t low 1.3 ? ? s scl scl "h" pulse width t high 0.6 ? ? s scl setup time for repeat "start" condition t su,sta 0.6 ? ? s scl,sda data hold time t hd,dat 0 ? ? ns scl,sda data setup time t su,dat 200 ? ? ns scl,sda setup time for "stop" condition t su,sto 0.6 ? ? s scl,sda bus free time between "stop" condition and "start" condition t buf 1.3 ? ? s scl data valid acknowledge time t vd,ack ? ? 1.2 s scl,sdaaack signal rise and fall time tir,tif ? ? (*3) s ? scl,sda data bus load capacitance cb ? ? 400 pf sda,sdaack noise pulse width tolerance t wf ? ? 50 ns scl,sda (*3) tir and tif shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=0.1 s.
fedl9479e-02 ML9479E 7/32 timing chart (osc1) osc1 (external clock) 1/f cp1 t wcp1 t wcp1 v ih v ih v il v il v ih t os c timing chart (serial interface) v ih v il v ih v il data clock v ih v ih v il v il v il v il load v ih v ih v il v il t wcp2 t wcp2 t hd t su 1/f cp2 t cl t lc t wld v ih v il t sf v ih v il t sr v ih t sr v ih v il t sf t sf t sr timing chart (i 2 c interface) t buf t low t vd;ack t r t f t hd;sta t hd;dat t high t su;dat t su;sto t su;sta sda scl sda v ih v il v ih v ih v il v ih v il v ih v ih v ih v ih v ih v il v il v il v il v il v ih v il
fedl9479e-02 ML9479E 8/32 reference data frame frequency characteristics vdd=5.5v/2.7v rf=470 ? frame frequency f frm = f osc /(16 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25% frame frequency characteristics rf=470k,vdd=5.5v 50 60 70 80 90 100 110 120 -60 -40 -20 0 20 40 60 80 100 120 temp ta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0) frame frequency characteristics rf=470k,vdd=2.7v 50 60 70 80 90 100 110 120 130 -60 -40 -20 0 20 40 60 80 100 120 tempta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0)
fedl9479e-02 ML9479E 9/32 power on/off timing to turn on the power supply, raise the logic power supply first, then lcd drive power supply in order to prevent the ic from malfunctioning. to fall the power supply, fall the lcd drive power supply first, then the logic power supply. for a vdd pin ranging from 0 v to vddmin, set vdd vlcd and t1 0 [ns]. to enable the internal poc circuit, the vdd power supply rise time t2 range needs to be 100 [s] ?? t2 ?? 500 [ms]. for the vdd power supply to turn off then turn on again, it is necessary to secure the poc discharge time t3 ?? 100 [ms]. initialization signal timing when resetb signal is externally input the resetb pin input is valid both for poceb = "l" and "h". usable in combination with the poc. keep the resetb pin at "l" level until the vdd reaches vddmin. (t4 200[ns]) when internal poc circuit is used w hen using the internal poc circuit in the initialization, set the poceb pin to "l". at this time, the power on/off timing conditions are t1 to t3 above mentioned. when resetb pin poc circuit is used if the power on/off timing conditions t1 to t3 cannot be kept, the resetb pin needs to have a capacitance to configure the poc circuit. for this case, connect a capacitance value according to the power supply rise time. for the power supply rise time t2 and external capacitance value, use the following formula as a guide: c rst [f] > t2 [sec] (30 10 3 ) v dd v lcd time voltage t1 t1 0.9v dd t2 v dd t3 v dd resetb vil t4 v dd min
fedl9479e-02 ML9479E 10/32 pin descriptions pad number symbol i/o description 109-112 m/s i this is the input to switch between the master and slave modes. it has a schmitt circuit. when this pin is "h", the mode is master. when this pin is "l", the mode is slave. 9-12 13-16 duty0 duty1 *1 i display duty switch pins. these have schmitt circuits. duty0="l", duty1="l" : static (com1=com2=com3=com4) duty0="h", duty1="l" : 1/2duty (com1=com3, com2=com4) duty0="l", duty1="h" : 1/3duty (com2=com4) duty0="h", duty1="h" : 1/4duty 121-124 bias i this pin sets the lcd bias. it has a schmitt circuit. bias="l": 1/3bias bias= "h" : 1/2bias 25-28 sa0 i slave address input pin. it has a schmitt circuit. 17-20 21-24 a1 a0 i sub address input pins. these have schmitt circuits. 117-120 osc i/e i this input selects whether to use the external clock input mode or to use the internal oscillation mode or external oscillation mode. it has a schmitt circuit. when this pin is "h", the mode is the internal or external rf oscillation mode. when this pin is "l", the mode is the external clock input mode. use the slave chip as it is connected to gnd. 78-82 83-87 88-82 osc1, oscr, osc2 *2 i i o these pins are for the oscillator circuit to generate common signals. the osc1 and oscr pins are input pins and have a schmitt circuit. osc2 is an output pin. it becomes an output when the osc i/e pin = "h" and a high impedance when the osc i/e pin = "l". in the master mode (m/s pin ="h") three types are selectable: internal oscillation mode, external oscillation mode, and external clock input mode. ?internal oscillation mode: set the osc i/e pin to "h", short the oscr and osc2 pins, and open the osc1 pin. ?external rf oscillation mode: set the osc i/e pin to "h", connect an oscillation resistor rf between the osc1 and osc2 pins, and open the oscr pin. ?external clock input mode: set the osc i/e pin to "l", open the oscr and osc2 pins, and input the external clock to the osc1 pin. in the slave mode (m/s pin ="l") open the oscr and osc2 pins and connect the osc1 pin to the ML9479E's cko pin that has been set to the master mode. 93-97 cko o clock output pin. in the master mode (m/s pin = "h"), the 1/16 division signal of the oscillation frequency is output. in the slave mode (m/s pin = "l"), the output is fixed to "l". for a cascade connection, connect this pin to the osc1 pin of the chip that has been set to the slave mode.
fedl9479e-02 ML9479E 11/32 98-102 syncb i/o input/output pin for common synchronization. it has a schmitt circuit. it becomes the synchronization signal output pin in the master mode (m/s pin = "h"). it becomes the synchronization signal input pin in the slave mode (m/s pin = "l"). for cascade connection, connect all of the involved ML9479Es' sync pins by the common line. 105-108 i2c i interface switching pin. it has a schmitt circuit. when this pin is "h", the interface is i 2 c. when this pin is "l", the interface is three-wire serial. 36-40 data (sda) i display data input pin. it has a schmitt circuit. i2c="l": serial interface; data input the display data in the order of seg160, seg159, ... , seg2, and seg1. the display data turns on at "h" and turns off at "l". i2c="h": i 2 c interface; sda input the display data in units of 8 bits. the display data turns on at "h" and turns off at "l". this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 41-45 clock (scl) i shift clock input pin for display data. it has a schmitt circuit. i2c="l": serial interface; clock the display data input to the data pin is serially input to the shift register at the clock signal rise. i2c="h": i 2 c interface; scl the display data input to the sda pin is serially input to the shift register at the scl signal rise. this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 46-50 load i input pin for the load signal of display data. it has a schmitt circuit. i2c="l": serial interface; load the display data in the shift register is transmitted as is to the segment driver for the "h" duration. when this pin is brought into "l", the shift register is disconnected from the segment driver. the display data in the shift register immediately before it become "l" is held in the data latch and transmitted to the segment driver. i2c="h": i 2 c interface use this pin as it is connected to gnd. 31-35 sdaack o i2c="l": serial interface use this pin as it is opened. i2c="h": i 2 c interface the i 2 c bus acknowledge output signal. normally, use it as it is connected with the sda pin. connect an external pull-up resistor whenever necessary, as it is an open drain pin. the pull-up connection destination supply voltage shall be the v dd supply voltage or less. 113-116 poceb i internal poc circuit enable pin. it has a schmitt circuit. when this pin is "h", the poc circuit becomes off and the constant current (8a) is cut. the resetb pin pull-up resistor is cut as well. when this pin is "l", the poc circuit becomes on. the resetb pin is connected to a pull-up resistor. 73-77 resetb *3 i reset signal input pin for initializing inside the ic. it has a schmitt circuit. the "l" level enables the reset. this pin has an internal pull-up resistor. open when poceb = "h". pull-up when poceb = "l". the power-on reset operation is available by connecting an external capacitor.
fedl9479e-02 ML9479E 12/32 125-128 129-132 test1 test2 i pin for testing the ic. these have internal pull-down resistors. use it as it is connected to gnd. 155-234 239-318 seg1 ? seg160 o outputs for lcd display. connected to the segment pins on the lcd panel. in the display off mode, all the outputs are fixed to gnd. 143-146 235-238 326-329 com1 ? com4 o outputs for lcd display. connected to the common pin on the lcd panel. the output pins are located at three positions: both ends of the chip and between seg80 and seg81. each is connected inside the chip. use the com pins in accordance with the panel to be used. in the display off mode, all the outputs are fixed to gnd. when the slave is set (m/s=?l?), connecting syncb signals enables the master chip to synchronize with common outputs. 59-65 vdd - power supply pin for logic circuit. 66-72 vlcd - power supply pin for lcd driver. 51-58 gnd - ground pin. 29-30 103-104 vddo - vdd output pin. use this pin when fixing the mode setting input pin to "h" on the cog. 7-8 133-134 gndo - ground output pin. use this pin when fixing the mode setting input pin to "l" on the cog. 1-6 135-142 147-154 319-325 330-331 dummy - floating pin. at this time, avoid this pin from shorting with pins other than dummy in the wiring on the cog. *1: for details of the com and seg waveform when a duty is selected, refer to "common waveform" on page 18 and "common segment waveform" on page 19 to 23. *2: oscillator circuit configuration ? when m/s = "h", osc i/e = "h" [internal rf oscillation mode] [external rf oscillation mode] open osc2 osc1 oscr osc2 r osc1 open oscr
fedl9479e-02 ML9479E 13/32 ? external clock input mode when m/s = "h" and osc i/e = "l" ? m/s = "l", slave mode, external clock input mode *3: reset circuit configuration ? external input to restb when poceb = "h" resetb vdd external input ? poc circuit configuration when poceb = "l" resetb vdd c rst osc2 osc1 open oscr open external clock osc2 osc1 op en oscr op en master cko
fedl9479e-02 ML9479E 14/32 description operation description (seria l interface) ? display data input as described in the data configuration section, the displa y data consists of the data field that corresponds to each segment on/off and the command field that indicates the display data input. when inputting the display data, the "f3" command is set in the command field. when the "f1" or "f2" command is set in the command field, the display data in the data field becomes invalid. the data input to the data pin is loaded to the shift register at the clock pulse rise, transferred to the display data latch during the load pulse at the "h" level, then output via the segment driver. d1 d2 d3 d4 d160 c0 c1 c2 c3 c4 c5 c6 clock data new data load display output c7 data field old data command field ? display on, display off the display becomes off at power-on reset. to display, write the display on command. the display off is the command that makes all segments off. writing the display off command, turns off the lights regardless of the display data. the display on is the command to release the display off. writing the display on command returns the display to the original state. d1 d2 c6 c4 c5 c6 c7 c4 c5 c6 c7 clock data load display on/off c7 reset display data input display on command write display off command write
fedl9479e-02 ML9479E 15/32 list of commands command name c7 c6 c5 c4 c3 c2 c1 c0 operation f0 0 0 0 0 x x x x disabled f1 0 1 f1 (*2) f0 (*2) x x x x frame frequency setting (f1,f0)=(0, 0): 65hz (f1,f0)=(0, 1): 75hz (f1,f0)=(1, 0): 85hz (f1,f0)=(1, 1): 95hz (valid for internal cr oscillation) f2 1 0 1 d (*2) x x x x display on/off "0" : off com=seg=gnd "1" : on f3(*1) 1 1 sa1 sa0 a1 a0 co1 co0 data write address setting (co1,co0)=(0, 0): corresponding to common 1 (co1,co0)=(0, 1): corresponding to common 2 (co1,co0)=(1, 0): corresponding to common 3 (co1,co0)=(1, 1): corresponding to common 4 sa1, sa0, a1, a0: chip address x: don't care (*1): for the i 2 c interface, sa0 is set at a slave address. these bits become "don't care". in the ML9479E, set the sa1 address to "1". (*2): the register is set to the following value by the resetb = "l" input or by the power-on poc. f1="0", f0="0", d="0" data configuration ? data configuration (serial interface) d160 d159 d158 d3 d2 d1 c0 c1 c2c3 c4 c5 command lcd display data corresponding to seg1 corresponding to seg160 first bit c6 c7 note 1 : the commands f1 and f2 settings become valid when the least four bits of c4 to c7 are input. (the bits from d1 to d160 and from c0 to c3 are not necessary.) note 2 : if the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side. note 3 : the command execution follows the contents of the c7 to c0 registers immediately before the load becomes "h".
fedl9479e-02 ML9479E 16/32 ? data configuration (i 2 c interface) for the i 2 c interface, each ic is assigned with a 7-bit slave address. the first one byte in the transfer consists of this 7-bit slave address and the r/w bit that indicates the data transfer direction. always input "0" to the eighth r/w bit because the ML9479E is a write-only lsi. the eight bits next to the slave address is a control byte. the first one bit is co: consecutive command setting bit and the next one bit is rs: command/data setting bit (the remaining six bits are the don't care bits). when co = "0": means the last control byte. when co = "1": means the control bytes are successively input. when rs = "0": means the data to be input next is the command data. when rs = "1": means the data to be input next is the display data. the display data can be successively input. example of data setting ? when inputting two commands ? when inputting the command and display data r/w s 01 1001 sa0 0 a co rs a msb lsb p salve address: 0 1 1 0 0 1 co: consecutive control byte setting bit 0: last control b y te , 1: consecutive control b y te rs: command/data settin g bi t 0: command data, 1: display data slave address control byte data/command when inputting two commands s 01 1001 sa0 0 a 10 aa 00 aa p command command s 01 1001 sa0 0 a 10 aa 01 aaa aaap display data display data command display data display data
fedl9479e-02 ML9479E 17/32 data write method ? serial interface the data is written to the address set by the data write setting command (f3). for the serial interface, the data is written in units of 160 bits. written from d160 to seg1, d159 to seg2, ... , d2 to seg159, and d1 to seg160. ? i 2 c interface the data is written to the address set by the slave address. for the i 2 c interface, the data is written to the specified address starting with the lsb side in units of 8 bits. (the data is written in the order from seg153-160, seg145-seg152, ... , seg9-16, and seg1-seg8.) msb segment output lsb 1234 72 73 74 75 76 77 78 79 80 com1 d160 d159 d158 d157 d89 d88 d87 d86 d85 d84 d83 d82 d81 com2 d160 d159 d158 d157 d89 d88 d87 d86 d85 d84 d83 d82 d81 com3 d160 d159 d158 d157 d89 d88 d87 d86 d85 d84 d83 d82 d81 com4 d160 d159 d158 d157 d89 d88 d87 d86 d85 d84 d83 d82 d81 msb segment output lsb 81 82 83 84 152 153 154 155 156 157 158 159 160 com1 d80 d79 d78 d77 d9 d8 d7 d6 d5 d4 d3 d2 d1 com2 d80 d79 d78 d77 d9 d8 d7 d6 d5 d4 d3 d2 d1 com3 d80 d79 d78 d77 d9 d8 d7 d6 d5 d4 d3 d2 d1 com4 d80 d79 d78 d77 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb segment output msb 1234 72 73 74 75 76 77 78 79 80 com1 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com2 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com3 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com4 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 lsb segment output msb 81 82 83 84 152 153 154 155 156 157 158 159 160 com1 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com2 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com3 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com4 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8
fedl9479e-02 ML9479E 18/32 v lcd gnd v lcd gnd v lcd /2 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd v lcd /2 ? common waveforms a t 1/2-bias com4 com1 com2 com4 com3 com1 com2 com1 com3 com3 com1 com3 com2 com4 com2 com4 com1 4 (1) at static (2) at 1/2-duty a t 1/3-bias (3) at 1/3-duty (4) at 1/4-duty
fedl9479e-02 ML9479E 19/32 common segment output wavefor m ?at static display example on com1 off com1 com2 com3 com4 seg2 seg3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9479e-02 ML9479E 20/32 common and segment output waveforms ? at 1/2dut y , 1/2bias display example com1 on com2 off seg2 seg3 com1 com3 com2 com4 seg1 s e g 1 s e g 2 s e g 3 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2
fedl9479e-02 ML9479E 21/32 common segment output wavefor m ?at 1/2 duty1/3bias display example com1 on com2 off seg2 seg3 com1 com3 com2 com4 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9479e-02 ML9479E 22/32 common and segment output waveforms ? at 1/3duty, 1/3bias display example com1 on com2 off com3 seg com1 com2 com4 com3 seg1 seg2 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9479e-02 ML9479E 23/32 common and se g ment out p ut waveforms ? at 1/4duty, 1/3bias display example com1 com2 on com3 off com4 seg2 seg3 com4 com1 com2 com3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9479e-02 ML9479E 24/32 example of application circuit cascade configuration 1 serial in terface internal cr oscillator circuit used 1/4duty resetb pin + external capacitance connection to configure poc circuit the common waveform of master and slave chip is active. [external component] cp = 0.1 [f] (bypass capacitor between power supplies) crst = 4.7 [f] (capacitance for external poc circuit) m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg160 com2 com3 com4 cko data ml9479d mater) gnd test2 m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg160 com2 com3 com4 cko data ml9479d (slave) gnd test2 5v 5v 5v 5v open open open open open open cpu lcd panel1/4duty 160 segment cp cp cp cp crst crst poceb poceb lcd panel1/4duty 160 segemnet ML9479E ML9479E
fedl9479e-02 ML9479E 25/32 cascade configuration 2 ii 2 c interface external rf-based cr oscillator circuit used 1/4duty external resetb signal input the common waveform of slave chip is open. [external component] cp = 0.1 [f] (bypass capacitor between power supplies), rf = 470 [k ? ] (external r, resistor for cr oscillator circuit), rup = resistor for sda data bus pull-up m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg160 com2 com3 com4 cko sda ml9479d master) gnd test2 m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg160 com2 com3 com4 cko sda ml9479d (slave) gnd test2 5v 5v open open open open cpu lcd panel1/4duty 160 n segment open rf 5v 5v 5v cp cp cp cp poceb rup poceb ML9479E ML9479E
fedl9479e-02 ML9479E 26/32 pad configuration pad layout (pattern face) c hip size : 8.84 mm x 0.90 mm chip thickness : 400 ? m 20 ? m minimum bump pitch : 50 ? m bump height : 15 ? m 3 ? m 321 152 1 140 y x b a 322 151 331 141 (0,0) bump and alignment mark dimensions (pattern face) p ad no.1 ? 140 : 35 ? m x 72 ? m pad no.141 ? 331 : 30 ? m x 84 ? m alignment marks a and b : see below [mark a] [mark b] alignment mark x-coordinate ( ? m) y-coordinate ( ? m) mark a 4308.9 -312.1 mark b -4305.9 305.9 aluminum (top metal) passivation 30 m 30 m 30 m 30 m 30 m 30 m aluminum (top metal) passivation 47 m 55 m 47 m 55 m coordinate position coordinate position
fedl9479e-02 ML9479E 27/32 pad center coordinates pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) 1 dummy -4236.2 -312.1 40 data(sda) -1863 -312.1 2 dummy -4176.2 -312.1 41 clock(scl) -1767.8 -312.1 3 dummy -4116.2 -312.1 42 clock(scl) -1711.8 -312.1 4 dummy -4056.2 -312.1 43 clock(scl) -1655.8 -312.1 5 dummy -3996.2 -312.1 44 clock(scl) -1599.8 -312.1 6 dummy -3936.2 -312.1 45 clock(scl) -1543.8 -312.1 7 gndo -3871 -312.1 46 load -1448.6 -312.1 8 gndo -3815 -312.1 47 load -1392.6 -312.1 9 duty1 -3749 -312.1 48 load -1336.6 -312.1 10 duty1 -3693 -312.1 49 load -1280.6 -312.1 11 duty1 -3637 -312.1 50 load -1224.6 -312.1 12 duty1 -3581 -312.1 51 gnd -1154.4 -312.1 13 duty0 -3510.4 -312.1 52 gnd -1084.2 -312.1 14 duty0 -3454.4 -312.1 53 gnd -1028.2 -312.1 15 duty0 -3398.4 -312.1 54 gnd -972.2 -312.1 16 duty0 -3342.4 -312.1 55 gnd -916.2 -312.1 17 a0 -3272 -312.1 56 gnd -860.2 -312.1 18 a0 -3216 -312.1 57 gnd -804.2 -312.1 19 a0 -3160 -312.1 58 gnd -748.2 -312.1 20 a0 -3104 -312.1 59 vdd -653 -312.1 21 a1 -3033.8 -312.1 60 vdd -597 -312.1 22 a1 -2977.8 -312.1 61 vdd -541 -312.1 23 a1 -2921.8 -312.1 62 vdd -485 -312.1 24 a1 -2865.8 -312.1 63 vdd -429 -312.1 25 sa0 -2795.6 -312.1 64 vdd -373 -312.1 26 sa0 -2739.6 -312.1 65 vdd -317 -312.1 27 sa0 -2683.6 -312.1 66 vlcd -221.8 -312.1 28 sa0 -2627.6 -312.1 67 vlcd -165.8 -312.1 29 vddo -2557.4 -312.1 68 vlcd -109.8 -312.1 30 vddo -2501.4 -312.1 69 vlcd -53.8 -312.1 31 sdaack -2406.2 -312.1 70 vlcd 2.2 -312.1 32 sdaack -2350.2 -312.1 71 vlcd 58.2 -312.1 33 sdaack -2294.2 -312.1 72 vlcd 114.2 -312.1 34 sdaack -2238.2 -312.1 73 resetb 209.6 -312.1 35 sdaack -2182.2 -312.1 74 resetb 265.6 -312.1 36 data(sda) -2087 -312.1 75 resetb 321.6 -312.1 37 data(sda) -2031 -312.1 76 resetb 377.6 -312.1 38 data(sda) -1975 -312.1 77 resetb 433.6 -312.1 39 data(sda) -1919 -312.1 78 osc1 503.8 -312.1
fedl9479e-02 ML9479E 28/32 pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) 79 osc1 559.8 -312.1 124 bias 3251.4 -312.1 80 osc1 615.8 -312.1 125 test2 3321.6 -312.1 81 osc1 671.8 -312.1 126 test2 3377.6 -312.1 82 osc1 727.8 -312.1 127 test2 3433.6 -312.1 83 osc2 790.4 -312.1 128 test2 3489.6 -312.1 84 osc2 846.4 -312.1 129 test1 3559.8 -312.1 85 osc2 902.4 -312.1 130 test1 3615.8 -312.1 86 osc2 958.4 -312.1 131 test1 3671.8 -312.1 87 osc2 1014.4 -312.1 132 test1 3727.8 -312.1 88 oscr 1090.4 -312.1 133 gndo 3798 -312.1 89 oscr 1146.4 -312.1 134 gndo 3854 -312.1 90 oscr 1202.4 -312.1 135 dummy 3924.2 -312.1 91 oscr 1258.4 -312.1 136 dummy 3984.2 -312.1 92 oscr 1314.4 -312.1 137 dummy 4044.2 -312.1 93 cko 1389.8 -312.1 138 dummy 4104.2 -312.1 94 cko 1445.8 -312.1 139 dummy 4164.2 -312.1 95 cko 1501.8 -312.1 140 dummy 4224.2 -312.1 96 cko 1557.8 -312.1 141 dummy 4308.9 -232.2 97 cko 1613.8 -312.1 142 dummy 4308.9 -182.2 98 syncb 1694 -312.1 143 com1 4308.9 -132.2 99 syncb 1750 -312.1 144 com2 4308.9 -82.2 100 syncb 1806 -312.1 145 com3 4308.9 -32.2 101 syncb 1862 -312.1 146 com4 4308.9 17.8 102 syncb 1918 -312.1 147 dummy 4308.9 67.8 103 vddo 2004.4 -312.1 148 dummy 4308.9 117.8 104 vddo 2060.4 -312.1 149 dummy 4308.9 167.8 105 i2c 2130.6 -312.1 150 dummy 4308.9 217.8 106 i2c 2186.6 -312.1 151 dummy 4308.9 267.8 107 i2c 2242.6 -312.1 152 dummy 4225 308.9 108 i2c 2298.6 -312.1 153 dummy 4175 308.9 109 m/s 2368.8 -312.1 154 dummy 4125 308.9 110 m/s 2424.8 -312.1 155 seg1 4075 308.9 111 m/s 2480.8 -312.1 156 seg2 4025 308.9 112 m/s 2536.8 -312.1 157 seg3 3975 308.9 113 poceb 2607 -312.1 158 seg4 3925 308.9 114 poceb 2663 -312.1 159 seg5 3875 308.9 115 poceb 2719 -312.1 160 seg6 3825 308.9 116 poceb 2775 -312.1 161 seg7 3775 308.9 117 osci/e 2845.2 -312.1 162 seg8 3725 308.9 118 osci/e 2901.2 -312.1 163 seg9 3675 308.9 119 osci/e 2957.2 -312.1 164 seg10 3625 308.9 120 osci/e 3013.2 -312.1 165 seg11 3575 308.9 121 bias 3083.4 -312.1 166 seg12 3525 308.9 122 bias 3139.4 -312.1 167 seg13 3475 308.9 123 bias 3195.4 -312.1 168 seg14 3425 308.9
fedl9479e-02 ML9479E 29/32 pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) 169 seg15 3375 308.9 214 seg60 1125 308.9 170 seg16 3325 308.9 215 seg61 1075 308.9 171 seg17 3275 308.9 216 seg62 1025 308.9 172 seg18 3225 308.9 217 seg63 975 308.9 173 seg19 3175 308.9 218 seg64 925 308.9 174 seg20 3125 308.9 219 seg65 875 308.9 175 seg21 3075 308.9 220 seg66 825 308.9 176 seg22 3025 308.9 221 seg67 775 308.9 177 seg23 2975 308.9 222 seg68 725 308.9 178 seg24 2925 308.9 223 seg69 675 308.9 179 seg25 2875 308.9 224 seg70 625 308.9 180 seg26 2825 308.9 225 seg71 575 308.9 181 seg27 2775 308.9 226 seg72 525 308.9 182 seg28 2725 308.9 227 seg73 475 308.9 183 seg29 2675 308.9 228 seg74 425 308.9 184 seg30 2625 308.9 229 seg75 375 308.9 185 seg31 2575 308.9 230 seg76 325 308.9 186 seg32 2525 308.9 231 seg77 275 308.9 187 seg33 2475 308.9 232 seg78 225 308.9 188 seg34 2425 308.9 233 seg79 175 308.9 189 seg35 2375 308.9 234 seg80 125 308.9 190 seg36 2325 308.9 235 com1 75 308.9 191 seg37 2275 308.9 236 com2 25 308.9 192 seg38 2225 308.9 237 com3 -25 308.9 193 seg39 2175 308.9 238 com4 -75 308.9 194 seg40 2125 308.9 239 seg81 -125 308.9 195 seg41 2075 308.9 240 seg82 -175 308.9 196 seg42 2025 308.9 241 seg83 -225 308.9 197 seg43 1975 308.9 242 seg84 -275 308.9 198 seg44 1925 308.9 243 seg85 -325 308.9 199 seg45 1875 308.9 244 seg86 -375 308.9 200 seg46 1825 308.9 245 seg87 -425 308.9 201 seg47 1775 308.9 246 seg88 -475 308.9 202 seg48 1725 308.9 247 seg89 -525 308.9 203 seg49 1675 308.9 248 seg90 -575 308.9 204 seg50 1625 308.9 249 seg91 -625 308.9 205 seg51 1575 308.9 250 seg92 -675 308.9 206 seg52 1525 308.9 251 seg93 -725 308.9 207 seg53 1475 308.9 252 seg94 -775 308.9 208 seg54 1425 308.9 253 seg95 -825 308.9 209 seg55 1375 308.9 254 seg96 -875 308.9 210 seg56 1325 308.9 255 seg97 -925 308.9 211 seg57 1275 308.9 256 seg98 -975 308.9 212 seg58 1225 308.9 257 seg99 -1025 308.9 213 seg59 1175 308.9 258 seg100 -1075 308.9 259 seg101 -1125 308.9 304 seg146 -3375 308.9 260 seg102 -1175 308.9 305 seg147 -3425 308.9 261 seg103 -1225 308.9 306 seg148 -3475 308.9 262 seg104 -1275 308.9 307 seg149 -3525 308.9
fedl9479e-02 ML9479E 30/32 pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) pad number pad name x-coordinate ( ? m) y-coordinate ( ? m) 263 seg105 -1325 308.9 308 seg150 -3575 308.9 264 seg106 -1375 308.9 309 seg151 -3625 308.9 265 seg107 -1425 308.9 310 seg152 -3675 308.9 266 seg108 -1475 308.9 311 seg153 -3725 308.9 267 seg109 -1525 308.9 312 seg154 -3775 308.9 268 seg110 -1575 308.9 313 seg155 -3825 308.9 269 seg111 -1625 308.9 314 seg156 -3875 308.9 270 seg112 -1675 308.9 315 seg157 -3925 308.9 271 seg113 -1725 308.9 316 seg158 -3975 308.9 272 seg114 -1775 308.9 317 seg159 -4025 308.9 273 seg115 -1825 308.9 318 seg160 -4075 308.9 274 seg116 -1875 308.9 319 dummy -4125 308.9 275 seg117 -1925 308.9 320 dummy -4175 308.9 276 seg118 -1975 308.9 321 dummy -4225 308.9 277 seg119 -2025 308.9 322 dummy -4308.9 203.2 278 seg120 -2075 308.9 323 dummy -4308.9 153.2 279 seg121 -2125 308.9 324 dummy -4308.9 103.2 280 seg122 -2175 308.9 325 dummy -4308.9 53.2 281 seg123 -2225 308.9 326 com4 -4308.9 3.2 282 seg124 -2275 308.9 327 com3 -4308.9 -46.8 283 seg125 -2325 308.9 328 com2 -4308.9 -96.8 284 seg126 -2375 308.9 329 com1 -4308.9 -146.8 285 seg127 -2425 308.9 330 dummy -4308.9 -196.8 286 seg128 -2475 308.9 331 dummy -4308.9 -246.8 287 seg129 -2525 308.9 288 seg130 -2575 308.9 289 seg131 -2625 308.9 290 seg132 -2675 308.9 291 seg133 -2725 308.9 292 seg134 -2775 308.9 293 seg135 -2825 308.9 294 seg136 -2875 308.9 295 seg137 -2925 308.9 296 seg138 -2975 308.9 297 seg139 -3025 308.9 298 seg140 -3075 308.9 299 seg141 -3125 308.9 300 seg142 -3175 308.9 301 seg143 -3225 308.9 302 seg144 -3275 308.9 303 seg145 -3325 308.9
fedl9479e-02 ML9479E 31/32 revision history page document no. issue date previous edition new edition description fedl9479e-01 may. 28,2012 ? ? final edition 1 issued fedl9479e-02 apr. 3,2013 10 10 bias="l": 1/2bias bias="h": 1/2bias
fedl9479e-02 ML9479E 32/32 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsib ility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human in jury (such as a medical instrument, transportation equipment, aerospace machinery, nucl ear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for an y such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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